1. Field of the Invention
A method of manufacturing a capacitor deep trench and of etching a deep trench opening is provided in the present invention, where, more particularly, the method forms an STI first, and then etches the deep trench opening.
2. Description of the Prior Art
The miniaturization of various electrical products is a recent trend. In current semiconductor integrated circuits manufacturing, the memory cell and the high speed logic circuit elements of a dynamic random access memory (DRAM) are integrated in one chip. This creates an embedded dynamic random access memory (EDRAM), which combines the memory array and logic circuits to decrease the area of the chip and increase the speed of dealing with data.
The DRAM needs to be designed to suit the high accumulation and high density, so a capacitor deep trench is currently applied to the high density DRAM. The manufacturing method of the capacitor deep trench includes etching a deep trench (DT) in a semiconductor substrate, and forming a buried plate, a capacitor dielectric layer and a poly-silicon conductive layer. There is shallow trench isolation (STI) to insulate the capacitor deep trench and the adjacent capacitor deep trench. Therefore, the size of the memory cell becomes smaller and the chip space is well arranged.
Please refer to FIGS. 1-4. FIGS. 1-4 are diagrams of the manufacture of the capacitor deep trench and STI according to the prior art. As FIG. 1 shows, a semiconductor chip 10 is divided into a logic area 16 and a memory array area 14. In FIG. 1, the memory array area 14 of the semiconductor chip 10 has a plurality of capacitor deep trenches 18. In general, the capacitor deep trench 18 manufacture includes etching the deep trench opening (not shown) in the silicon substrate 12 by a silicon oxide layer 19 and a silicon nitride layer 20 as a hard mask. Then, a buried plate, (not shown), which is the storage node of the capacitor deep trench 18 for a storage electron or hole is formed in the opening of the silicon substrate 12 by arsenic silicate glass (ASG) diffusion. Then, the capacitor dielectric layer 22 is formed in the opening of the silicon substrate 12 by doping and thermal oxidation processes. Finally, a conductive layer is filled in the opening as a capacitor lower electrode 24, and the capacitor deep trench 18 is finished. The capacitor dielectric layer 22 is made from silicon oxide, silicon nitride, and silicon oxide (ONO). The capacitor lower electrode 24 is made from poly-silicon filled in the deep trench opening (not shown).
Next, as FIG. 2 shows, the silicon nitride layer 20 is smeared with a photo resist layer. The photo resist layer is patterned by the prior PEP, and is backed to form a photo resist mask which defines the memory array area 14 of the STI photo resist opening 30 and the logic area 16 of the STI photo resist opening 32.
As FIG. 3 shows, a plasma dry etching process is provided. For example: the etcher is set, the top power is 600 watts (W), and the bottom power is 100 W. Tetrafluoromethane (CF4) is a reactive gas and passes 80 standard cubic centimeters per minute (sccm) every minute. The photo resist mask is an etching mask and the silicon nitride layer 20 is etched from the STI photo resist opening 30, 32. Then, the reaction condition of the etcher is reset. The top power is 500 watts (W), and the bottom power is 60 W. Sulfur Hexafluoride (SF6) is a reactive gas and passes 18 sccm/min. Oxygen (O2) passes 14 sccm/min and Helium (He) passes 100 sccm/min to help the reaction. The silicon oxide layer 19, the silicon substrate 12, part of the capacitor lower electrode 24 and part of the capacitor dielectric layer 22 are etched by the STI photo resist opening 30, 32 to form the STI opening 34 in the memory array area 14 and the STI opening 36 of the logic area 16 at the same time. It should be mentioned that when the silicon oxide layer 19, the silicon substrate 12 and part of the capacitor dielectric layer 22 are etched, He can be utilized to remove the polymer caused by the etching process to avoid the polymer affecting the etching effect.
Finally, as FIG. 4 shows, a trench insulation material is filled in the memory array area 14 of the STI opening 34 and the logic area 16 of the STI opening 36. The trench insulation material is flattened by CMP. The STI 38 of capacitor deep trench 18 is finished.
Please refer to FIG. 5. FIG. 5 is a diagram of the capacitor dielectric layer etched incompletely according to the prior art. As FIG. 5 shows, because forming the STI opening 34requires etching the silicon nitride layer 20, the silicon oxide layer 19, the silicon substrate 12, part of the capacitor lower electrode 24, and part of the capacitor dielectric layer 22 firstly, then, the silicon substrate 12 can form part of the STI opening 34. However, the capacitor dielectric layer 22 is made from a silicon oxide, silicon nitride, silicon oxide layer (ONO), and the hard mask of the deep trench opening is also made from the silicon nitride, therefore the etching process has a poor effect on the ONO capacitor dielectric layer 22. The part of the capacitor dielectric layer 22 is etched incompletely causing the capacitor dielectric layer residue 52, and the STI opening 34 to be damaged.
The manufacture of the capacitor deep trench and STI in the prior art forms the capacitor deep trench firstly, and then forms the STI, where the STI opening of the logic area, and the memory array area in the semiconductor chip are made together. The STI opening of the logic area is only formed on the silicon substrate. Forming the STI opening of the memory array area requires etching the partial capacitor deep trench, making it difficult to control the STI opening plasma etching process, so capacitor dielectric layer residue occurs. Another problem that can occur is, when the logic area and the memory array area are etched for the STI opening, the uniform and position of the STI opening etching in the logic area can be affected, and a complex computer program is needed to amend the etching process. Even more etching processes are processed to form the STI opening of the logic area and the memory array area individually.
Because the prior art has the above-mentioned shortcomings, how to invent a better etching process to form the STI opening of the logic area and the memory area is an important issue.